Non-linear D/a Converters for Direct Digital Frequency Synthesizers

By Zhihe Zhou, Ph.D. Washington State University August 2006 Chair: George S. La Rue We investigated the design and implementation of non-linear D/A converters (DAC) for a direct digital frequency synthesizer (DDFS), which consists of a phase accumulator, a phase-to-sine look-up table and a DAC. Using a non-linear DAC can significantly reduce the look-up table size, hence, reducing the power dissipation and enabling highspeed phase-to-sine conversion. A non-linear DAC with 12-bit resolution was designed and fabricated on Honeywell MOI5 0.35 μm SOI process. It implements a 32-segment piece-wise linear approximation to a sine function. The non-linear DAC is uniquely designed to implement multiplication using a high-speed analog method. The look-up table is reduced from 11K bits to 544 bits. Test shows the non-linear DAC can operate up to 600 MHz. The spurious-free dynamic range (SFDR) is up to 72 dBc and the radiation tolerance is 200 Krad Si. Another 14-bit non-linear DAC was also designed and fabricated on a commercial 0.18 μm CMOS process. This non-linear DAC implements a 16-segment piecewise quadratic approximation and is used in a DDFS with 14-bit phase resolution, achieving even higher memory compression ratio. The target operation speed is 2 GHz and the SFDR is anticipated to be over 80 dBc.